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[Other resource] ramlib_06

Description: 这是一个有关FIFO的VHDL 程序。。。请大家下载分享。
Platform: | Size: 578254 | Author: 张亚伟 | Hits:

[Other resource] fifo_VHDL

Description: FIFO的源代码，详细描述FIFO的工作原理和过程，用VHDL编写。
Platform: | Size: 9086 | Author: 胡志敏 | Hits:

[Other resource] video_fifo

Description: 有关视频方面的fifo设计,vhdl编写
Platform: | Size: 2165 | Author: 曾工 | Hits:

[Other resource] fifo8_8

Description: 8*8位的fifo数据缓冲器的vhdl源程序。经过quartus ii 6.0 验证成功。
Platform: | Size: 1088 | Author: 李松 | Hits:

[Other resource] generalFIFO

Description: 通用FIFO的VHDL编程 字深和字长可以自己设计
Platform: | Size: 1089 | Author: danny | Hits:

[Other resource] 16×4bitFIFO

Description: 16×4bit的FIFO设计,VHDL语言编的的，能在ISE上仿真出来结果。
Platform: | Size: 4491 | Author: 张军 | Hits:

[Other resource] sram

Description: FPGA向SRAM中写入数据(VHDL编程)，包含通用fifo，sram等
Platform: | Size: 270755 | Author: 王刚 | Hits:

[Other resource] asyn_FIFOrealizedbyVHDL

Description: 一个比较经典的用VHDL实现的FIFO论文
Platform: | Size: 53245 | Author: Roger | Hits:

[Other resource] uart_regs

Description: 可以直接下载到芯片用的带有FIFO的完全UART程序，vhdl语言编写。
Platform: | Size: 388297 | Author: liujingxing | Hits:

[USB develop] usb

Description: 使用68013的测试程序，包含68013固件程序（采用slave FIFO bulk同步读写，EP2 OUT，EP6 IN），驱动，PC端测试用程序。CPLD的VHDL代码
Platform: | Size: 1012462 | Author: 李华 | Hits:

[VHDL-FPGA-Verilog] my_fifo_vhdl

Description: XILINX的FPGA实现的双口ram源码，可作为dsp\SDRAM和pci桥接作用，可直接使用，实际工程通过。-XILINX FPGA Implementation of the dual-port ram source, as dsp \ SDRAM and pci bridge, and can be used directly, through practical projects.
Platform: | Size: 19456 | Author: 朱效志 | Hits:

[VHDL-FPGA-Verilog] sopc_avalon_audio_dac_fifo

Description: fpga嵌入式系统组件，可以很方便的扩展，是个实例的例子，可以实现歌曲播放-FPGA embedded system components, it is easy to expand, is an example of the example, you can realize music player
Platform: | Size: 14336 | Author: dahai | Hits:

[VHDL-FPGA-Verilog] zzmodelsim

Description: verilog仿真工具modelsim的使用教程,幻灯片形式的,图文并茂,简单易学.经典的老教材-ModelSim Verilog simulation tool use tutorials, slide the form of illustrations, easy to learn. classic old material
Platform: | Size: 505856 | Author: oasis | Hits:

[VHDL-FPGA-Verilog] an_dcfifo_top_restored

Description: alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输 ，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
Platform: | Size: 928768 | Author: alison | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-verilog

Description: SDRAM的vegilog代码，做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块-SDRAM
Platform: | Size: 717824 | Author: 吴厚航 | Hits:

[VHDL-FPGA-Verilog] VGA-VerilogHDL

Description: 用Verilog HDL编写的VGA显示驱动程序-Verilog HDL prepared with VGA display driver
Platform: | Size: 141312 | Author: liping | Hits:

[Graph Recognize] lcd-code

Description: 比较完整的LCD接口代码，verilog编写，分为6800和8080两种CPU接口，且有完整的仿真程序-Relatively complete LCD interface code, verilog prepared 6800 and 8080 is divided into two types of CPU interfaces, and there is a complete simulation program
Platform: | Size: 1831936 | Author: 李佳 | Hits:

[VHDL-FPGA-Verilog] mini_fifo

Description: 另外一个用VHDL源码编写的FIFO模块程序,可以比较一下和FIFO有什么区别.-Another, prepared by using VHDL source FIFO module procedures, you can compare and What is the difference between FIFO.
Platform: | Size: 2048 | Author: falcon_cq | Hits:

[Software Engineering] 00837024

Description: 一个基于VHDL同步FIFO的设计思路的文章，以及一个编译完整的程序。-VHDL-based synchronous FIFO design ideas article, as well as a compiler procedures.
Platform: | Size: 224256 | Author: 飞仔 | Hits:

[VHDL-FPGA-Verilog] FIFO_EMIF

Description: 实现FPGA通过EMIF总线给DSP定期发送数据的功能-FPGA implementation through the EMIF bus regularly send data to the DSP function
Platform: | Size: 1480704 | Author: 徐成发 | Hits:
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